1. Field of the Invention
The invention relates to an SOS substrate having a low defect density in the vicinity of an interface.
2. Description of Related Art
Conventionally, a silicon-on-sapphire (SOS) substrate containing sapphire having a high insulation property, a low dielectric loss and a high thermal conductivity as a handle substrate has come into practical use since 1960s. The SOS substrate is an oldest silicon-on-insulator (SOI) substrate and forms an SOI structure by heteroepitaxially growing silicon on an R surface (1012) of sapphire.
However, recently, an SOI using a SIMOX method, the bonding method and the like has become a main stream. Although the SOS substrate, which is an SOI substrate having silicon on a sapphire substrate, cannot cope, the SOS substrate has been used only for a device such as a high frequency device requiring a low dielectric loss. It is known that since a heteroepitaxial SOS substrate is formed by heteroepitaxially growing silicon on sapphire of which lattice constant is 12% different from that of silicon, many defects due to the mismatch of lattice magnitude are generated (see, for example, Non-Patent Document 1).
Recently, use of a mobile communication represented by a mobile phone has been widely spread so that a demand for a high frequency device has been increased. i Use of an SOS substrate has been considered in this field. However, use of the heteroepitaxial SOS substrate is limited to small individual parts such as a switch at present since a defect density is high.
It has been reported that the surface defect density of the heteroepitaxial SOS substrate is about 109 pieces/cm2 in a Secco defect detection method (a mixed solution of K2Cr2O7 or Cr2O3 and HF), a selective etching defect detection method (a mixed solution of HF, KI, I and CH3OH) or the like (see, for example, Non-Patent Document 1).
To reduce the defects of the heteroepitaxial SOS substrate, there is proposed a method comprising the steps of ion-implanting high concentration Si in the vicinity of the interface between a Si film and a sapphire substrate, making a remaining Si surface amorphous, and anneal at about 600° C. to gradually recrystallize an amorphous layer from a surface side having a less amount of defects. This method is called a single solid phase growth. Further, there is also proposed a method of repeating the above method twice for trying to reduce defects further (see, for example, Yoshii et al. Japanese Journal of Applied Physics, Vol. 21 (1982) Supplement 21-1, pp. 175-179). This method is called a double solid phase growth.
However, even if the double solid phase growth method is used, the defect density is about 106 to 107 pieces/cm2 so that it is difficult to make a recent highly downscaled and sophisticated device. Further, it is also difficult to make a relatively large size device such as a system chip having many arithmetic processing functions. It can be said that this is due to an essential problem of the heteroepitaxial growth (an epitaxial growth of materials having different lattice constants).
Moreover, it is shown in Yoshii et al. Japanese Journal of Applied Physics, Vol. 21 (1982) Supplement 21-1, pp. 175-179 that the defect density becomes larger at a site closer to a sapphire/silicon interface which is a growth interface.